Currently, in order to improve performance of logic type semiconductor integrated circuits such as a microprocessor or an ASIC (Application Specific Integrated Circuit) or to implement memory type semiconductor integrated circuits having large capacity or the like, miniaturization for reducing the size thereof has been performed on semiconductor elements constituting these integrated circuits.
More specifically, in the miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) as semiconductor elements, fine lines (short channels) have been implemented in control gate electrodes, and at the same time, gate insulating films have been implemented as thin films. Accordingly, the problems occur in that an increase in a junction leak current, an increase in a random variation of a threshold value, and an increase in a gate tunnel leak current are caused due to a high concentration of channel impurities. In addition, although a technique of improving mobility of carriers in a channel by applying mechanical stress to a semiconductor element by using SiGe or the like is used in order to improve performance of the MOSFET element, this technique also has a problem in that a decrease in stress sensitivity or an increase in crystal defect is caused due to the progress of miniaturization of the semiconductor element.
Therefore, as a method of implementing high performance and low power consumption of MOSFET, research of transistors for implementing low power consumption by using a tunneling current, more specifically, a direct tunneling current rather than a diffusion current has been actively made. In a tunneling transistor using the tunneling current, it is possible to obtain a good gradient (sub-threshold slope) of a drain current with respect to a gate voltage in a sub-threshold range in transistor characteristics in comparison with a theoretical threshold value in the case using a diffusion current. Therefore, it is expected that it is possible to implement low power consumption.